Silicon large-scale integrated circuits, among other device technologies, are applied ubiquitously throughout modern society to accommodate the needs for digital information and digital control. An integrated circuit may be composed of a plurality of semiconductor devices, such as transistors or the like, which can be produced according to a variety of techniques. To facilitate increased integration and speed of semiconductor devices, a trend of continuously scaling semiconductors (e.g., reducing size and features of semiconductor devices) has emerged. Reducing semiconductor and/or semiconductor feature size provides improved speed, performance, density, cost per unit, etc., of resultant integrated circuits. However, as semiconductor devices and device features have become smaller, conventional fabrication techniques have become limited in their ability to produce finely defined features.
A particular development in the range of semiconductor devices are field effect transistors (FETs) where metal oxide semiconductor field effect transistors (MOSFET or MOS) and complimentary metal oxide semiconductor (CMOS) can utilize both p-type and n-type (PMOS and NMOS) transistors in conjunction with a gate structure(s). Of particular concern is the increased likelihood of a shortage occurring across a gate and a proximately located conductive element, such as a contact.
FIG. 49 illustrates an ideal scenario (continuous bold line) where a contact 950 (e.g., connecting with a trench silicide 920 forming a source/drain) is ideally located between replacement metal gate (RMG) structures 910a and 910b. In an embodiment, contact 950 may comprise of a self aligned contact (SAC), however such technology may not be amenable to RMG structures owing to the degree of positional tolerancing (±q) required that can be inherent to self aligned structure technology. A constraint regarding how far critical dimensioning can be reduced is where consideration has to be made with regard to the distance between a pair of structures when a subsequent structure is to be placed between the pair of structures. Further, as the distance between respective RMGs in a semiconductor device is reduced, as a function of scaling, the ability to accurately locate a contact, whether it be self aligning or otherwise, becomes difficult. For example, a pair of FET gates (e.g., gates 910a and 910b, which can be any combination pairing comprising a pair of nFET gates or a pair of pFET gates) are separated by a source/drain region (e.g., source/drain 920), where, in a subsequent operation, a contact has to be formed to connect with the source/drain region while not coming into contact with either of the FET gates 910a or 910b. 
For example, FIG. 50 illustrates an undesirable arrangement where contact 960 has been erroneously located and gate shortage can occur along electrical pathway S1. In another example, as illustrated in FIG. 51, even with the approach of utilizing a metal line 970 having a tapered profile, and while the metal line is located on source/drain region 920, the distance S2 between the gate 910a and the interconnect 970 may be of such a short distance that current leakage can occur at S2.
Hence, as shown in FIGS. 50 and 51, owing to the diminished sizes with which semiconductor devices are being manufactured, the ability to accurately locate contact(s) with respect to other device features (e.g., RMGs) is being tested. Hence, while technologies facilitate further miniaturization of semiconductor related devices and components, issues regarding construction of the devices (e.g., gate formation, surface profiles, etc.) are still to be addressed.